/*******************************************************************************
 *                                    ZLG
 *                         ----------------------------
 *                         innovating embedded platform
 *
 * Copyright (c) 2001-present Guangzhou ZHIYUAN Electronics Co., Ltd.
 * All rights reserved.
 *
 * Contact information:
 * web site:    https://www.zlg.cn
 *******************************************************************************/
#ifndef __HPM6E00_TSW_H__
#define __HPM6E00_TSW_H__

#ifdef __cplusplus
extern "C" {
#endif  /* __cplusplus*/
#include "core/include/hpm6e00_clk.h"
#include "core/include/hpm6e00_regs_tsw.h"
#include "common/hpm_common.h"
#include "common/hpm_errno.h"
#include <stdint.h>
#include <stdio.h>

#ifndef TSW_MM2S_DMA_WAIT_CBUFF_TIMEOUT
#define TSW_MM2S_DMA_WAIT_CBUFF_TIMEOUT   (1000U)
#endif

#ifndef TSW_MM2S_DMA_CHECK_RBUFE_TIMEOUT
#define TSW_MM2S_DMA_CHECK_RBUFE_TIMEOUT  (1000U)
#endif

#define TSW_SOC_SHAP_MAX_CL_ENTRIES                (256U)

#ifndef TSW_BUS_FREQ
#define TSW_BUS_FREQ        (100000000UL)
#endif

#ifndef TSW_NS_IN_ONE_SEC
#define TSW_NS_IN_ONE_SEC   (1000000000UL)
#endif

/* \brief RXFIFO 寄存器组索引 */
#define TSW_RXFIFO_E1     (0UL)
#define TSW_RXFIFO_P1     (1UL)

/* \brief TSN 端口寄存器组索引 */
#define TSW_TSNPORT_PORT1 (0UL)
#define TSW_TSNPORT_PORT2 (1UL)
#define TSW_TSNPORT_PORT3 (2UL)

/* \brief MAC 地址低位与高位 */
#define MAC_LO(mac) (uint32_t)(mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24))
#define MAC_HI(mac) (uint32_t)(mac[4] | (mac[5] << 8))


#define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_POS) & TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_MASK)
#define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_POS)

#define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_POS) & TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_MASK)
#define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_POS)

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_POS) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_MASK)
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_POS)

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_POS) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_MASK)
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_POS)

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_POS) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_MASK)
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_POS)

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_POS) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_MASK)
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_POS)

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_POS) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_MASK)
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_POS)

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_POS) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_MASK)

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_POS) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_MASK)

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_POS) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_MASK)

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_POS) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_MASK)

#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_POS)

#define TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_POS)

#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_POS) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_MASK)
#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_POS)

#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_POS) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_MASK)
#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_POS)

#define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_POS) & TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_MASK)
#define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_MASK) >> TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_POS)

#define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_POS) & TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_MASK)
#define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_POS)

#define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_POS) & TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_MASK)
#define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_MASK) >> TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_POS)

#define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_POS) & TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_MASK)
#define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_MASK) >> TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_POS)

#define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_POS) & TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_MASK)
#define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_POS)

#define TSW_MM2S_DMA_CR_MXLEN_SET(x) (((uint32_t)(x) << TSW_MM2S_DMA_CR_MXLEN_POS) & TSW_MM2S_DMA_CR_MXLEN_MASK)
#define TSW_MM2S_DMA_CR_MXLEN_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CR_MXLEN_MASK) >> TSW_MM2S_DMA_CR_MXLEN_POS)
#define TSW_MM2S_DMA_CR_IRQEN_SET(x) (((uint32_t)(x) << TSW_MM2S_DMA_CR_IRQEN_POS) & TSW_MM2S_DMA_CR_IRQEN_MASK)
#define TSW_MM2S_DMA_CR_IRQEN_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CR_IRQEN_MASK) >> TSW_MM2S_DMA_CR_IRQEN_POS)
#define TSW_MM2S_DMA_CR_SOE_SET(x)   (((uint32_t)(x) << TSW_MM2S_DMA_CR_SOE_POS) & TSW_MM2S_DMA_CR_SOE_MASK)
#define TSW_MM2S_DMA_CR_SOE_GET(x)   (((uint32_t)(x) & TSW_MM2S_DMA_CR_SOE_MASK) >> TSW_MM2S_DMA_CR_SOE_POS)

#define TSW_MM2S_DMA_SR_RBUFE_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_RBUFE_MASK) >> TSW_MM2S_DMA_SR_RBUFE_POS)
#define TSW_MM2S_DMA_SR_CBUFF_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_CBUFF_MASK) >> TSW_MM2S_DMA_SR_CBUFF_POS)
#define TSW_MM2S_DMA_SR_RSET_GET(x)  (((uint32_t)(x) & TSW_MM2S_DMA_SR_RSET_MASK) >> TSW_MM2S_DMA_SR_RSET_POS)

#define TSW_MM2S_CTRL_ID_SET(x) (((uint32_t)(x) << TSW_MM2S_CTRL_ID_POS) & TSW_MM2S_CTRL_ID_MASK)
#define TSW_MM2S_CTRL_ID_GET(x) (((uint32_t)(x) & TSW_MM2S_CTRL_ID_MASK) >> TSW_MM2S_CTRL_ID_POS)

#define TSW_MM2S_RESP_DECERR_GET(x) (((uint32_t)(x) & TSW_MM2S_RESP_DECERR_MASK) >> TSW_MM2S_RESP_DECERR_POS)
#define TSW_MM2S_RESP_SLVERR_GET(x) (((uint32_t)(x) & TSW_MM2S_RESP_SLVERR_MASK) >> TSW_MM2S_RESP_SLVERR_POS)
#define TSW_MM2S_RESP_ID_GET(x)     (((uint32_t)(x) & TSW_MM2S_RESP_ID_MASK) >> TSW_MM2S_RESP_ID_POS)

#define TSW_S2MM_DMA_SR_IRQ_SET(x) (((uint32_t)(x) << TSW_S2MM_DMA_SR_IRQ_POS) & TSW_S2MM_DMA_SR_IRQ_MASK)
#define TSW_S2MM_DMA_SR_IRQ_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_IRQ_MASK) >> TSW_S2MM_DMA_SR_IRQ_POS)

#define TSW_S2MM_DMA_CR_MXLEN_SET(x) (((uint32_t)(x) << TSW_S2MM_DMA_CR_MXLEN_POS) & TSW_S2MM_DMA_CR_MXLEN_MASK)
#define TSW_S2MM_DMA_CR_MXLEN_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CR_MXLEN_MASK) >> TSW_S2MM_DMA_CR_MXLEN_POS)
#define TSW_S2MM_DMA_CR_IRQEN_SET(x) (((uint32_t)(x) << TSW_S2MM_DMA_CR_IRQEN_POS) & TSW_S2MM_DMA_CR_IRQEN_MASK)
#define TSW_S2MM_DMA_CR_IRQEN_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CR_IRQEN_MASK) >> TSW_S2MM_DMA_CR_IRQEN_POS)
#define TSW_S2MM_DMA_CR_SOE_SET(x)   (((uint32_t)(x) << TSW_S2MM_DMA_CR_SOE_POS) & TSW_S2MM_DMA_CR_SOE_MASK)
#define TSW_S2MM_DMA_CR_SOE_GET(x)   (((uint32_t)(x) & TSW_S2MM_DMA_CR_SOE_MASK) >> TSW_S2MM_DMA_CR_SOE_POS)
#define TSW_S2MM_DMA_SR_RSET_GET(x)  (((uint32_t)(x) & TSW_S2MM_DMA_SR_RSET_MASK) >> TSW_S2MM_DMA_SR_RSET_POS)

#define TSW_S2MM_RESP_DECERR_GET(x) (((uint32_t)(x) & TSW_S2MM_RESP_DECERR_MASK) >> TSW_S2MM_RESP_DECERR_POS)
#define TSW_S2MM_RESP_SLVERR_GET(x) (((uint32_t)(x) & TSW_S2MM_RESP_SLVERR_MASK) >> TSW_S2MM_RESP_SLVERR_POS)
#define TSW_S2MM_RESP_ID_GET(x)     (((uint32_t)(x) & TSW_S2MM_RESP_ID_MASK) >> TSW_S2MM_RESP_ID_POS)
#define TSW_S2MM_RESP_LENGTH_GET(x) (((uint32_t)(x) & TSW_S2MM_RESP_LENGTH_MASK) >> TSW_S2MM_RESP_LENGTH_POS)

#define TSW_S2MM_CTRL_ID_SET(x) (((uint32_t)(x) << TSW_S2MM_CTRL_ID_POS) & TSW_S2MM_CTRL_ID_MASK)
#define TSW_S2MM_CTRL_ID_GET(x) (((uint32_t)(x) & TSW_S2MM_CTRL_ID_MASK) >> TSW_S2MM_CTRL_ID_POS)

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_POS)
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_SET(x)     (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_POS) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_MASK)
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_GET(x)     (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_POS)

#define TSW_TSNPORT_MXTK_TICK_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MXTK_TICK_POS) & TSW_TSNPORT_MXTK_TICK_MASK)
#define TSW_TSNPORT_MXTK_TICK_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MXTK_TICK_MASK) >> TSW_TSNPORT_MXTK_TICK_POS)

#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_POS) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_MASK)
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_MASK) >> TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_POS)
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_POS) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_MASK)
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_MASK) >> TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_POS)

#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_POS) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_MASK)
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_MASK) >> TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_POS)

#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_POS) & TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_MASK)
#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_POS)

#define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_POS) & TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_MASK)
#define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_POS)

#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_POS) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_MASK)
#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_POS)

#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_POS) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_MASK)
#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_POS)

#define TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_SET(x) (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_POS) & TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_MASK)
#define TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_GET(x) (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_MASK) >> TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_POS)

#define TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SET(x) (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_POS) & TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_MASK)
#define TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_GET(x) (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_MASK) >> TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_POS)

#define TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_SET(x) (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_POS) & TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_MASK)
#define TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_GET(x) (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_MASK) >> TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_POS)
#define TSW_APB2AXI_CAM_REQDATA_0_TYPE_SET(x) (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_0_TYPE_POS) & TSW_APB2AXI_CAM_REQDATA_0_TYPE_MASK)
#define TSW_APB2AXI_CAM_REQDATA_0_TYPE_GET(x) (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_0_TYPE_MASK) >> TSW_APB2AXI_CAM_REQDATA_0_TYPE_POS)
#define TSW_APB2AXI_CAM_REQDATA_0_CH_SET(x) (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_0_CH_POS) & TSW_APB2AXI_CAM_REQDATA_0_CH_MASK)
#define TSW_APB2AXI_CAM_REQDATA_0_CH_GET(x) (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_0_CH_MASK) >> TSW_APB2AXI_CAM_REQDATA_0_CH_POS)

#define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SET(x)    (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_POS) & TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_MASK)
#define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_GET(x)    (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_POS)
#define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_POS) & TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_MASK)
#define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_POS)

#define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SET(x)  (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_POS) & TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_MASK)
#define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_GET(x)  (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_POS)
#define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SET(x)  (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_POS) & TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_MASK)
#define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_GET(x)  (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_POS)
#define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SET(x)  (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_POS) & TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_MASK)
#define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_GET(x)  (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_POS)
#define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_POS) & TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_MASK)
#define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_POS)
#define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SET(x)  (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_POS) & TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_MASK)
#define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_GET(x)  (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_POS)

#define TSW_APB2AXIS_ALMEM_STS_RDY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_STS_RDY_MASK) >> TSW_APB2AXIS_ALMEM_STS_RDY_POS)

#define TSW_APB2AXI_CAM_REQDATA_2_VID_SET(x) (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_2_VID_POS) & TSW_APB2AXI_CAM_REQDATA_2_VID_MASK)
#define TSW_APB2AXI_CAM_REQDATA_2_VID_GET(x) (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_2_VID_MASK) >> TSW_APB2AXI_CAM_REQDATA_2_VID_POS)

#define MAC_MDIO_CTRL_OP_WR (0x01)
#define MAC_MDIO_CTRL_OP_RD (0x02)

typedef enum {
    tsw_mac_type_emac = 0,
    tsw_mac_type_pmac
} tsw_mac_type_t;

typedef enum {
  tsw_mac_mode_mii = 0,
  tsw_mac_mode_gmii
} tsw_mac_mode_t;

typedef enum hpm_dma_port{
    TSN_DMA_PORT_AUTO = 0x00,
    TSN_DMA_PORT_0    = 0x01,
    TSN_DMA_PORT_1    = 0x02,
    TSN_DMA_PORT_2    = 0x03,
    TSN_DMA_PORT_ALL  = 0x80
} tsw_dma_port_t;

typedef enum {
  tsw_port_phy_itf_mii   = 0,
  tsw_port_phy_itf_rmii  = 4,
  tsw_port_phy_itf_rgmii = 1
} tsw_port_phy_itf_t;

struct tsw_tas_controllist_entry {
    uint8_t     state;      /**< gate state vector */
    uint8_t     op;         /**< gate operation code (set, set-and-hold, set-and-release) */
    uint32_t    interval;   /**< interval time in nanoseconds */
};

struct tsw_tas_config {
    struct tsw_tas_controllist_entry *p_entry;
    uint32_t                          entry_count;
    uint32_t                          cycle_time;     /**< cycle length in nanoseconds */
    uint32_t                          base_time_ns;   /**< based on real time */
    uint32_t                          base_time_sec;  /**< based on real time */
};

/* \brief TSW DMA 配置结构体 */
struct tsw_dma_config {
    uint8_t soe;
    uint8_t irq;
    uint8_t maxlen;
};

/* \brief TSW 帧结构体 */
struct tsw_frame {
  uint8_t   id;
  uint8_t  *p_buf;
  uint16_t  len;
};

/**
 * \brief TSW 设置端口时钟延时
 *
 * @param port   设置的端口
 * @param tx_dly tx 时钟延迟线延时值
 * @param rx_dly rx 时钟延迟线延时值
 *
 * @return 成功返回 0
 */
int tsw_port_clk_delay_set(uint8_t port, uint8_t tx_dly, uint8_t rx_dly);
void tsw_rtc_time_increment_set(uint32_t increment);
/**
 * \brief TSW 使能 MAC 控制
 *
 * @param port     设置的端口
 * @param mac_type MAC 类型
 *
 * @return 成功返回 0
 */
int tsw_ep_mac_ctrl_enable(uint8_t port, tsw_mac_type_t mac_type);
/**
 * \brief TSW 关闭 MAC 控制
 *
 * @param port     设置的端口
 * @param mac_type MAC 类型
 *
 * @return 成功返回 0
 */
int tsw_ep_disable_mac_ctrl(uint8_t        port,
                            tsw_mac_type_t mac_type);
/**
 * \brief TSW 使能所有 MAC 控制
 *
 * @param mac_type MAC 类型
 */
void tsw_ep_all_mac_ctrl_enable(tsw_mac_type_t mac_type);
/**
 * \brief TSW 关闭所有 MAC 控制
 *
 * @param mac_type MAC 类型
 */
void tsw_ep_all_mac_ctrl_disable(tsw_mac_type_t mac_type);

void tsw_cam_clear(void);
void tsw_cam_vlan_port_set(void);
/**
 * \brief 设置 TSW 端口 MAC 模式
 *
 * @param port 设置的端口
 * @param mode MAC 地址
 *
 * @return 成功返回 0
 */
int tsw_ep_mac_mode_set(uint8_t port, tsw_mac_mode_t mode);
/**
 * \brief 设置 TSW 端口 MAC 地址
 *
 * @param port       设置的端口
 * @param p_mac_addr MAC 地址
 * @param is_promisc 是否启用启用了混杂模式
 *
 * @return 成功返回 0
 */
int tsw_ep_mac_addr_set(uint8_t port, uint8_t *p_mac_addr, bool_t is_promisc);
/**
 * \brief TSW 端口接口设置
 *
 * @param port 相关端口
 * @param itf  接口模式
 *
 * @return 成功返回 0
 */
int tsw_port_interface_set(uint8_t port, tsw_port_phy_itf_t itf);
/**
 * \brief TSW 设置 MDIO 配置
 *
 * @param port    相关端口
 * @param clk_div 时钟分频
 *
 * @return 成功返回 0
 */
int tsw_ep_mdio_cfg_set(uint8_t port, uint8_t clk_div);
/**
 * \brief TSW MDIO 读函数
 *
 * @param port     相关端口
 * @param phy_addr PHY 设备地址
 * @param reg_addr PHY 设备要读的寄存器地址
 * @param p_data   存储读取的数据
 *
 * @return 成功返回 0
 */
int tsw_ep_mdio_read(uint8_t   port,
                     uint32_t  phy_addr,
                     uint32_t  reg_addr,
                     uint16_t *p_data);
/**
 * \brief TSW MDIO 写函数
 *
 * @param port     相关端口
 * @param phy_addr PHY 设备地址
 * @param reg_addr PHY 设备要写的寄存器地址
 * @param data     要写的数据
 *
 * @return 成功返回 0
 */
int tsw_ep_mdio_write(uint8_t  port,
                      uint32_t phy_addr,
                      uint32_t reg_addr,
                      uint16_t data);
/**
 * \brief TSW 获取默认的 DMA 配置
 *
 * @param p_config DMA 配置结构体
 */
void tsw_default_dma_cfg_get(struct tsw_dma_config *p_config);
/**
 * \brief TSW 发送初始化
 *
 * @param p_config DMA 配置结构体
 *
 * @return 成功返回 0
 */
int tsw_send_init(struct tsw_dma_config *p_config);
/**
 * \brief TSW 接收初始化
 *
 * @param p_config DMA 配置结构体
 *
 * @return 成功返回 0
 */
int tsw_recv_init(struct tsw_dma_config *p_config);
/**
 * \brief TSW 帧发送函数
 *
 * @param p_buf   要发送的缓存
 * @param buf_len 要发送的缓存长度
 * @param id      DMA 通道 ID
 *
 * @return 成功返回 0
 */
int tsw_frame_send(uint8_t *p_buf, uint16_t buf_len, uint8_t id);
/**
 * \brief TSW 帧发送并且检查响应函数
 *
 * @param p_buf   要发送的缓存
 * @param buf_len 要发送的缓存长度
 * @param id      DMA 通道 ID
 *
 * @return 成功返回 0
 */
int tsw_frame_send_chk_resp(uint8_t *p_buf, uint16_t buf_len, uint8_t id);
/**
 * \brief TSW 提交接收描述
 *
 * @param p_buf   提交的接收缓存的地址
 * @param buf_len 提交的接收缓存的长度
 * @param id      绑定缓存的 DMA ID
 *
 * @return 成功返回 0
 */
int tsw_commit_recv_desc(uint8_t *p_buf, uint16_t buf_len, uint8_t id);
/**
 * \brief TSW 帧接收函数
 *
 * @param p_frame TSW 帧结构体
 *
 * @return 成功返回 0
 */
int tsw_frame_recv(struct tsw_frame *p_frame);
void tsw_lookup_table_set(uint16_t entry_num, uint8_t dest_port, uint64_t dest_mac);
#ifdef __cplusplus
}
#endif  /* __cplusplus  */
#endif


